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A low power technology mapping method for Adaptive Logic Module

By: Wei Chen; Nakamura, Y.; Yoshimura, T.; Xiaolin Zhang;

2011 / IEEE / 978-1-4577-1740-6

Description

This item was taken from the IEEE Conference ' A low power technology mapping method for Adaptive Logic Module ' In this paper, we propose a novel mapping method for FPGA with dual-output LUT based logic elements (LEs), aiming for power reduction. Recently, a new kind of LE-Adaptive Logic Module (ALM), which contains a dual-output fracturable LUT instead of traditional single-output K-LUT, is used in Altera's high-end FPGA products to obtain a good trade-off between area and delay. To map a design to ALMs, we introduce a LUT-merging step after K-LUT technology mapping, where the LUTs are merged into ALMs. We propose a max-weight matching based method for the LUT-merging, trying to reduce the number of used ALMs and meanwhile reduce power consumption. Experimental results show that, compared with a previous LUT-merging method for area-optimization, though resulting in a little more ALMs, our low power LUT-merging method improves the power by 7.48%.