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Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm
2011 / IEEE / 978-1-4577-1785-7
This item was taken from the IEEE Conference ' Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm ' We measures and investigate the correlation between well potential and SEUs to effectively detect SEUs by well potential perturbation. Cell-based perturbation detectors are implemented adjacent to FFs constructed a shift register. They measures the locations of voltage levels over 0.6 or 0.8 V. The measurement results by neutron irradiation on a 65nm bulk CMOS shows that almost 90% of SEUs are generated without any well potential perturbation. We also shows that the well-potential elevation over 0.8 V activates bipolar actions on neighbourhood transistors which prevents SEUs.
Well-potential Perturbation Detectors
Cell-based Perturbation Detectors
Size 65 Nm
Integrated Circuit Modeling
Voltage 0.8 V
Cmos Logic Circuits