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Integration of a plasma doping PULSION� process into a fully depleted SOI transistor flow chart
By: Milesi, F.; Felch, S.; Torregrosa, F.; Etienne, H.; Yckache, K.; Gonzatti, F.; Duchaine, J.; Claverie, A.; Spiegel, Y.;
2011 / IEEE / 978-1-61284-134-2
This item was taken from the IEEE Conference ' Integration of a plasma doping PULSION� process into a fully depleted SOI transistor flow chart ' For continued scaling of future CMOS devices (sub-32 nm), heavily-doped ultra-shallow junctions are required. Plasma doping (PD) with PULSION� offers the attractive capability of high dose and low energy doping with short production times [1, 2]. All of these aspects make plasma doping a good candidate for the next technology steps driven by the roadmap. In this paper we discuss the integration of plasma doping into a Fully Depleted SOI CMOS process flow (sub-10 nm top Si layer). The compatibility of PD with patterns (charging effects) has been studied as well as the Selective Epitaxial Growth (SEG) performed after the source/drain extension implantations to thicken these regions prior to silicidation .
Scanning Electron Microscopy
Cmos Process Flow
Fully Depleted Soi Transistor Flow Chart
Plasma Doping Process
Selective Epitaxial Growth
Cmos Integrated Circuits