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Parasitic resistance reduction technology

By: Hobbs, C.; Loh, W.Y.; Ok, I.; Jammy, R.; Ang, K.-W.; Akarvardar, K.; Ngai, T.; Hung, P.Y.; Young, C.D.;

2011 / IEEE / 978-1-61284-134-2

Description

This item was taken from the IEEE Conference ' Parasitic resistance reduction technology ' We reported double-gate transistors with reduced source-drain (SD) resistance with aluminum (Al) implant on S/D for sub 22 nm technology node1. Al implanted S/D can provide to modulate the electron barrier height of PtSi towards the conduction band. We also investigate Schottky barrier modulation using a new Ge ion implantation (I/I) and segregation approach and the impact of spike anneal on the SBH tuning. Novel silcide alloys of Ni with Yb or Er can be adopted for a FinFET structure. These techniques attribute constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.