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Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

By: Tomizawa, H.; Chen, S.T.; Spooner, T.; Usui, T.; Colburn, M.; Arnold, J.; Vo, T.; Maniscalco, J.; van der Straten, O.; Sankarapandian, M.; Shobha, H.; Tagami, M.; Tsumura, K.; Burns, S.; Landie, G.; Koay, C.S.; Kelly, J.; Ishikawa, M.; Yin, Y.; Kato, H.; Horak, D.;

2011 / IEEE / 978-1-4577-0502-1

Description

This item was taken from the IEEE Conference ' Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme ' A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.