Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

By: Shyng-Tsong Chen; Tomizawa, H.; Spooner, T.; Usui, T.; Colburn, M.; Arnold, J.C.; Mclellan, E.; Scaduto, A.; Xu, Y.; Landie, G.; Kato, H.; Halle, S.; Burns, S.; Koay, C.-S.; Mignot, Y.; Ishikawa, M.; Horak, D.; Yin, Y.; Cohen, S.; Levin, T.; Canaperi, D.; Kelly, J.; Van der Straten, O.; Tsumura, K.; Tagami, M.; Shobha, H.; Sankarapandian, M.;

2011 / IEEE / 978-1-4577-0502-1

Description

This item was taken from the IEEE Conference ' 64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme ' This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.