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64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme
By: Shyng-Tsong Chen; Tomizawa, H.; Spooner, T.; Usui, T.; Colburn, M.; Arnold, J.C.; Mclellan, E.; Scaduto, A.; Xu, Y.; Landie, G.; Kato, H.; Halle, S.; Burns, S.; Koay, C.-S.; Mignot, Y.; Ishikawa, M.; Horak, D.; Yin, Y.; Cohen, S.; Levin, T.; Canaperi, D.; Kelly, J.; Van der Straten, O.; Tsumura, K.; Tagami, M.; Shobha, H.; Sankarapandian, M.;
2011 / IEEE / 978-1-4577-0502-1
This item was taken from the IEEE Conference ' 64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme ' This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.
Size 56 Nm
Size 64 Nm
Rie Trench Profile
Sav Litho/rie Scheme
Pitch Split Double Patterning Scheme
Pitch Split Double Exposure Patterning Scheme
Cu Dual-damascene Interconnects
Size 80 Nm
Integrated Circuit Interconnections