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Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps

By: Kriangsak, S.L.; Beleran, J.D.; Zhang, Y.F.; Yang, Y.B.; Wilson, P.L.O.; Au, K.Y.; Surasit, C.; Toh, C.H.; Drake, Y.S.K.;

2011 / IEEE / 978-1-61284-498-5

Description

This item was taken from the IEEE Conference ' Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps ' High performance, multi functional and package miniaturization will be the main driving forces that propel the future trend and development of fully integrated multi silicon dies stack using through silicon via (TSV) packaging technology. This paper serves as an extension of the foregoing paper, where TSV-micro C4 solder interconnect were used and stack up to 4-die compared to the 2-die stack previously demonstrated at ECTC 2010[3]. This study is driven by future requirement for memory dies stacking or multiple devices stacking on a thru silicon interposer (TSI). A TSI enables interconnect pitch matching between a high I/Os top chip and a low cost organic substrate however, extension to 4 die stack reveals many daunting assembly challenges for all backend assembly processes. This paper demonstrates with assistance from finite element analysis, actual process verification and reliability test, the required fundamental changes to material properties, bill of material (BOM) and assembly process manufacturability modification in order to achieve feasible assembly process and reliable performance for 4 thin die stacking to an organic substrate using a 1�solder re-flow process and standard flip chip machine in a mass production scenario. This achievement will further strengthen low cost high volume production capability for thru silicon stacking (TSS).