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3D interconnection process development and integration with low stress TSV
By: Khong, C.H.; Li, H.Y.; Ho, S.W.; Chua, T.T.; Toh, C.H.; Nathapong, S.; Liao, E.B.; Kriangsak, S.L.; Ng, C.; Pang, X.F.; Lim, L.S.; Lee, W.S.; Chew, S.P.;
2010 / IEEE / 978-1-4244-6412-8
Description
This item was taken from the IEEE Conference ' 3D interconnection process development and integration with low stress TSV ' The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling.
Related Topics
Tsv Plating Time
Chemical Mechanical Polishing
Cmp
Sidewall Plated Tsv
Wafer Warpage
Thermal-mechanical Simulation
Shear Reduction
Through-silicon Vias
Polymers
Filling
Copper
Thermal Stresses
Silicon
Robustness
Costs
Chemical Processes
Solids
Front-vial Expose
Copper Seed Deposition
Polymer Filling
Tsv Technology
Thru Silicon Via
3d Interconnection Process Development
Bending Stress
Polymers
Integrated Circuit Interconnections
Electronics Packaging
Chemical Mechanical Polishing
Bending Strength
Shear Deformation
Engineering
3d Interconnect Technology