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3D chip stacking & reliability using TSV-micro C4 solder interconnection
By: Zhu, W.H.; Zhang, X.R.; Kriangsak, S.L.; Au, K.Y.; Toh, C.H.;
2010 / IEEE / 978-1-4244-6412-8
This item was taken from the IEEE Conference ' 3D chip stacking & reliability using TSV-micro C4 solder interconnection ' Multi silicon dies stack using through silicon via (TSV) is required for higher performance, greater package miniaturization and more functionality electronic device. A through silicon interposer (TSI) enables interconnect pitch matching between a high I/Os top chip and a low cost organic substrate. TSI also mitigates the risk of extreme low-K (ELK) layers delamiantion. This paper demonstrates the process feasibility and reliability performance for multi thin die stacking on a strip organic substrate using a 1x solder re-flow process flow. Inline pressurized spray system with and without force flow were shown to be an effective flux cleaning method for stacked dies with ~35 um microgap. In a two dies stack fcCSP, the presence of a bottom TSI reduces top chip stress based on finite element simulation. A low CTE TSI results in a lower top chip stress than a high CTE TSI. Also, a reduction of top die thickness and/or an increase of package mold cap thickness result in a significant package warpage reduction. Micro C4 solder bumps joints with TiW/Cu/Ni under bumps metallization (UBM) and TiW/Cu/Ni/Au bond pad were reliable up to 1000 thermal cycles.
Integrated Circuit Reliability
Finite Element Simulation
3d Chip Stacking
3d Chip Reliability
Tsv-micro C4 Solder Interconnection
Through Silicon Via
Through Silicon Interposer
Extreme Low-k Layers Delamination
Finite Element Methods
Integrated Circuit Packaging
Integrated Circuit Interconnections
Finite Element Analysis
Three-dimensional Integrated Circuits
Multi Silicon Dies Stack