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Development of graphene FETs for high frequency electronics
By: Farmer, D.; Jenkins, K.; Yu-Ming Lin; Ek, B.; Valdes-Garcia, A.; Hsin-Ying Chiu; Chun-Yung Sung; Avouris, P.;
2009 / IEEE / 978-1-4244-5641-3
This item was taken from the IEEE Conference ' Development of graphene FETs for high frequency electronics ' Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequency electronics are reviewed. By improving the oxide deposition process and reducing series resistance, an intrinsic cut-off frequency as high as 50 GHz is achieved in a 350-nm-gate graphene FET at a drain bias of 0.8 V. This f
Voltage 0.8 V
Electrical Resistance Measurement
Field Effect Transistor
Intrinsic Cut Off Frequency
Oxide Deposition Process
Top Gated Graphene Fet
High Frequency Electronics
Size 350 Nm
Field Effect Transistors