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A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (�Flash), suitable for full 3D integration

By: Faynot, O.; De Salvo, B.; Ghibaudo, G.; Molas, G.; Carabasse, C.; Delaye, V.; Pauliac, S.; Baud, L.; Loup, V.; Hartmann, J.-M.; Colonna, J.-P.; Arvet, C.; Vizioz, C.; Maffini-Alvaro, V.; Tachi, K.; Nowak, E.; Hubert, A.; Ernst, T.;

2009 / IEEE / 978-1-4244-5641-3

Description

This item was taken from the IEEE Conference ' A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (�Flash), suitable for full 3D integration ' We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called �Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The �Flash exhibits up to 1.8V �VTh between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.