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A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation

By: Shimazaki, Y.; Maeda, N.; Morimoto, M.; Yamaoka, M.; Komatsu, S.; Osada, K.;

2009 / IEEE / 978-1-4244-4071-9

Description

This item was taken from the IEEE Conference ' A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation ' A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.