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Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

By: Cheng, K.; Khakifirooz, A.; O'Neill, J.; Doris, B.; Bu, H.; Kozlowski, P.; Sadana, D.; Wang, J.; Di, M.; Herman, J.; Smalley, M.; Levin, T.; Upham, A.; Johnson, R.; Zhu, Z.; Loesing, R.; Li, X.; Holt, J.; Jamison, P.; Seo, S.-C.; Haran, B.; Edge, L.F.; Furukawa, T.; Faltermeier, J.; Li, J.; Zhu, Y.; Adam, T.; Reznicek, A.; Schmitz, S.; Kulkarni, P.; Kanakasabapathy, S.;

2006 / IEEE / 978-1-4244-3308-7

Description

This item was taken from the IEEE Conference ' Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain ' A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200&��m. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2nm ETSOI. Even without strain boosters, a remarkable PFET drive current of 550�A/�m is achieved at Ioff = 3nA/�m, VDD = 0.9V with 6nm SOI channel and 25nm physical gate length. Shortchannel effects are well-controlled with DIBL less than 100mV/V and subthreshold swing less than 90mV/dec. A 15% reduction in parasitic capacitance is achieved by a faceted raised source/drain (RSD). Excellent electrostatics and small device dimensions render ETSOI devices suitable for 22-nm node and beyond.