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Efficient implementation of QRD-RLS algorithm using hardware-software co-design

By: Krishnamurthy, A.; Rai, N.; Lodha, N.; Venkataraman, H.;

2009 / IEEE / 978-1-4244-3751-1

Description

This item was taken from the IEEE Conference ' Efficient implementation of QRD-RLS algorithm using hardware-software co-design ' This paper presents the implementation of QR Decomposition based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA) using hardware-software co-design. The system has been implemented on Xilinx Spartan 3E FPGA with Microblaze soft core processor. The hardware part consists of a custom peripheral that solves the part of the algorithm with higher computational costs and the software part consists of an embedded soft core processor that manages the control functions and rest of the algorithm. The speed and flexibility of FPGAs render them viable for such computationally intensive application. This paper also presents the implementation results and their analysis.