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The path and challenges to 90nm radiation hardened technology
By: Kelly, A.; Doyle, S.; Chan, E.; Haddad, N.; Lawrence, R.; Ross, J.; Patel, D.; Lawson, D.;
2008 / IEEE / 978-1-4577-0482-6
Description
This item was taken from the IEEE Conference ' The path and challenges to 90nm radiation hardened technology ' Preliminary radiation effects analysis on a commercial 90nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.
Related Topics
Random Access Memory
Single Event Upset
Transistors
Cmos Integrated Circuits
Cmos Technology
Radiation Hardening
Integrated Circuit Modeling
Radiation Hardening By Design
Total Ionizing Dose
Single Event Effects
Single Event Latch-up
Radiation Hardening By Process
Low Power Space Applications
Radiation Hardness Enhancement
Cmos Process
Radiation Effects Analysis
Radiation Hardened Technology
Size 90 Nm
Cmos Integrated Circuits
Radiation Hardening (electronics)
Engineering
Hardness Potential
