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15nm-diameter 3D stacked nanowires with independent gates operation: �FET

By: Dupre, C.; Hubert, A.; Deleonibus, S.; Ernst, T.; Faynot, O.; Ghibaudo, G.; Guillaumot, B.; Rivallin, P.; Chevolleau, T.; Loup, V.; Pauliac, S.; Baud, L.; Rivoire, M.; Colonna, J.-P.; Becu, S.; Jublot, M.; Maffini-Alvaro, V.; Vizioz, C.; Aussenac, F.; Arvet, C.; Barnola, S.; Hartmann, J.-M.; Garnier, G.; Allain, F.;

2008 / IEEE / 978-1-4244-2377-4

Description

This item was taken from the IEEE Conference ' 15nm-diameter 3D stacked nanowires with independent gates operation: �FET ' For the first time, we report a 3D stacked sub-15nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named �FET. Extremely high driving currents for 3D-NWFET (6.5mA/�m for NMOS and 3.3mA/�m for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. �FET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82mV/dec. instead of 95mV/dec.). This highlights the better scalability of 3D-NWFET and �FET compared to FinFET and IG-FinFET, respectively.