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A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology
2008 / IEEE / 978-1-4244-2363-7
This item was taken from the IEEE Conference ' A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology ' This paper presents an innovative 3D CMOS 6T SRAM cell design in Multi-Channel (MC) FET technology by well adapting the number of channels per device. A simulation model for the 45nm MCFET has been developed based on silicon measurements. The electrical results validated by simulations, exhibit more than 25% power dissipation reduction and 17% cell stability improvement for the same area and read access time, when compared with a standard CMOS 6T SRAM cell designeds in 2D.
Power Dissipation Reduction
Random Access Memory
Silicon On Insulator Technology
Semiconductor Device Modeling
Field Effect Transistors
Cmos Memory Circuits