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Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond
By: Divakaruni, R.; Chu, S.; Quek, E.; Sudijono, J.; Li, Y.; Ng, H.; Shang, H.; Rovedo, N.; Kim, S.D.; Stierstorfer, R.; Li, J.; Belyansky, M.; Park, J.; Yan, J.; Robinson, R.; Kim, J.J.; Lee, Y.M.; Zhao, L.; Yuan, J.; Fang, S.; Tan, S.S.; Iyer, S.;
2008 / IEEE / 978-1-4244-1614-1
This item was taken from the IEEE Conference ' Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond ' A novel low cost technique to improve device performance by enhanced Stress Proximity Technique (eSPT) with Recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520uA/um at Ioff of 1nA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.
Germanium Silicon Alloys
Semiconductor Device Manufacture
Low Cost Processes
Enhanced Stress Proximity Technique
Stress Proximity Technique
Field Effect Transistors