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Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate

By: Yoshinaga, H.; Miyazaki, S.; Kurosawa, E.; Ohta, A.; Aminaka, T.; Sato, M.; Matsuki, T.; Kadoshima, M.; Ohji, Y.; Nara, Y.; Aoyama, T.; Yamada, K.; Yamabe, K.; Shiraishi, K.;

2007 / IEEE / 978-1-4244-1507-6

Description

This item was taken from the IEEE Conference ' Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate ' We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAlN gate HfAlSiON p-FET for hp 32 nm Low Standby Power (LSTP) CMOS devices. Low Vt of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AlN-cap formation of TiAlN and subsequent intermixing between AlN-cap and HfSiON by high temperature annealing. There was no degradation in gate leakage current and electron mobility in TaSiN gate HfSiON n-FET even if TaSiN was formed after TiAlN removal. Thus, this technique is practical for realizing dual-metal-gate dual-high-k CMOS devices.