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Impact of flash annealing on performance and reliability of high-�/metal-gate MOSFETs for sub-45 nm CMOS
By: Rino Choi; Man Chang; Harris, R.; Vora, N.; Kirsch, P.; Young, C.; Bersuker, G.; Heh, D.; Majhi, P.; Kalra, P.; Tsu-Jae King Liu; Jammy, R.; Hsing-Huang Tseng; Hyunsang Hwang; Joonmyoung Lee;
2007 / IEEE / 978-1-4244-1507-6
This item was taken from the IEEE Conference ' Impact of flash annealing on performance and reliability of high-�/metal-gate MOSFETs for sub-45 nm CMOS ' The use of millisecond annealing to meet ultra-shallow junction (USJ) requirements for sub-45 nm CMOS technologies is imperative. In this study, a detailed investigation of the effects of flash annealing on MOSFETs with Hf-based gate dielectric and metal gate electrodes is presented. The flash anneal process is found to be compatible with the high-�/metal gate stack, in terms of gate dielectric reliability, and effective to achieve the benefits of USJ. However, it can lead to significantly degraded MOSFET performance due to defect generation in the interfacial SiOx layer, unless a post-metallization anneal is performed.
High K Dielectric Materials
High-k Gate Dielectrics
Rapid Thermal Annealing
Size 45 Nm
Interfacial Siox Layer
Metal Gate Electrodes
Hf-based Gate Dielectric Reliability
Sub45 Nm Cmos Technology
Cmos Integrated Circuits
High-κ-metal-gate Mosfet Reliability