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A 28 mW, 1.5 V GPS receiver in 0.25 �m silicon-on-sapphire CMOS process

By: Dan, N.; Losser, D.; Adamski, J.; Pucci, G.; Fujita, K.; Kuramochi, T.;

2007 / IEEE / 978-2-87487-003-3

Description

This item was taken from the IEEE Conference ' A 28 mW, 1.5 V GPS receiver in 0.25 �m silicon-on-sapphire CMOS process ' This paper describes a 28 mW, 1.5 V Global Positioning System (GPS) radio receiver chip implemented in a 0.25 �m silicon-on-sapphire CMOS process. The receiver uses a low IF architecture and achieves a cascaded noise figure of 3.5 dB including the RF SAW filter. The design takes advantage of the matching network integration capabilities and superb isolation properties of Peregrine's UltraCMOStrade silicon-on-sapphire process technology.