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3D stacked channels: how series resistances can limit 3D devices performance

By: Vulliet, N.; Pouydebasque, A.; Guillaumot, B.; Ernst, T.; Bernard, E.; Deleonibus, S.; Skotnicki, T.; Coronel, P.; Souifi, A.; Maffini-Alvaro, V.; Delaye, V.; Borel, S.; Hartmann, J.M.; Kermarrec, O.; Campidelli, Y.; Vizioz, C.; Rivallin, P.; LeCarval, G.; Andrieu, F.;

2007 / IEEE / 978-1-4244-0879-5

Description

This item was taken from the IEEE Conference ' 3D stacked channels: how series resistances can limit 3D devices performance ' We have integrated 3D low power Multi-Channel Field Effect Transistors (MCFETs) with TiN/HfO2 gate stacks. We present, for the first time, a general analytical model explaining quantitatively the experimental current gain of this architecture compared to an optimized planar FD-SOI reference with the same gate stack. The gain is highly dependant on gate and drain voltages. The impact of the series resistances is also amplified in 3D devices. The number of channels and the S/D shape will have to be carefully chosen and optimized in order to minimize those resistances.