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High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

By: Luo, Z.; Rovedo, N.; Ieong, M.; Sudijono, J.; Ku, J.; Hierlemann, M.; Shang, H.; Ng, H.; Tian, C.; Yang, Z.; Vayshenker, A.; Lee, S.; Kim, S.; Lee, H.; Yuan, T.K.J.; Chan, V.; Han, J.; Holt, J.; Park, D.; Kwon, O.; Yan, J.; Fang, S.; Dyer, T.; Teo, L.; Ong, S.; Phoong, B.; Eller, M.; Utomo, H.; Ryou, C.; Wang, H.; Stierstorfer, R.; Clevenger, L.; Kim, S.; Toomey, J.; Sciacca, D.; Li, J.; Wille, W.; Zhao, L.;

2007 / IEEE / 978-4-900784-03-1

Description

This item was taken from the IEEE Conference ' High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology ' An aggressively scaled high performance 45nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at 1V, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.