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Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor
By: Hirose, K.; Yanagisawa, K.; Yasu, Y.; Mizuno, H.; Kanno, Y.; Irie, N.; Shimazaki, Y.; Hattori, T.; Irita, T.; Yamada, T.; Ishii, T.; Miyairi, Y.; Hoshi, T.;
2007 / IEEE / 1-4244-0756-7
This item was taken from the IEEE Conference ' Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor ' Hierarchical power distribution with a power tree has been developed. The key features are power tree management rules and a distributed common power-domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1,000,000-gate power domain were effectively reduced to 1/4,000 in multi-CPU SoCs with minimal area overhead.
Digital Signal Processing Chips
Large Scale Integration
Power Tree Management
Low-power Multi-cpu Processor
Hierarchical Power Distribution