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Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate
By: Taeho Lee; Kisik Choi; Jammy, R.; Byoung Hun Lee; Seung Chul Song; Barnett, J.; Choi, R.; Bersuker, G.; Young, C.; Seungsoo Kweon; Harris, H.R.;
2007 / IEEE / 1-4244-0918-7
This item was taken from the IEEE Conference ' Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate ' The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/ HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface with the Si substrate and the observed Vth shift has been attributed to the passivation of positively charged defects in the dielectric stack and additional negative charge associated with F atoms. Thermally grown interfacial layer combined with F implantation resulted in excellent device parameters and reliability as well as lower PMOS Vth due to inherently lower defect density and defect passivation effect by F atoms.
High K Dielectric Materials
High-k Gate Dielectrics
Atomic Layer Deposition
Bottom Interfacial Layer
Semiconductor Device Reliability