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Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

By: Mazor, D.; Blaikie, R.J.; Mulligan, D.J.; Bushnell, M.L.;

2007 / IEEE / 0-7695-2762-0

Description

This item was taken from the IEEE Conference ' Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors ' We improved Smith and Ahmed¿s nanowire singleelectron transistor (SET) to change its operating temperature from 4.2oK to room temperature. We made more than 1000 nanotechnology SETs on the fabrication line. We characterized their faults, the yield, the dependence of faults on the process, and the correlation between channel width and faults. We improved the SET process recipe. SETs are made on silicon-on-insulator (SOI) wafers using an E-beam lithography machine (the Raith 150) to create two L-shaped trenches in the Si; these are etched through to the SiO2 insulating layer using reactive ion etching (RIE). After process improvements, our yield was 24.3% working SETs, of which 79.4% had significant Coulomb oscillations at room temperature. Also, 20.6% of the SETs had stuck-open transistors, 50.7% had resistive bridges, and 4.4% had gross defects, from severe fabrication line contamination.