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Failure Mode Detection and Process Optimization for 65 nm CMOS Technology

By: Bonifield, T.; Jin Zhao; Olsen, L.; DeBord, J.R.D.; Lytle, S.;

2006 / IEEE / 978-4-9904138-0-4

Description

This item was taken from the IEEE Conference ' Failure Mode Detection and Process Optimization for 65 nm CMOS Technology ' Short loop test flows have been commonly used in back end of line (EOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the Shallow Trench Isolation (STI), Gate and Pre-Metal Dielectric (PMD)/Contact loops of a 65nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.