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Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices
By: Han, J.P.; Utomo, H.; Ieong, M.; Sudijono, J.; Ku, J.H.; Shum, D.; Hierlemann, M.; Amos, R.; Chiulli, G.; Lindsay, R.; Kim, S.D.; Loesing, R.; Burns, L.; Turansky, A.; Madan, A.; St Lawrence, B.; Davis, R.; Murphy, R.; Li, J.; Li, J.; Kim, J.J.; Zhuang, H.; Mishra, S.; Schepis, D.; Gutmann, A.; Teo, L.W.; Rovedo, N.; Luo, Z.; Krishnasamy, R.; Stierstorfer, R.; Chong, Y.F.; Fang, S.; Ng, H.; Holt, J.; Adam, T.N.; Kempisty, J.;
2006 / IEEE / 1-4244-0438-X
This item was taken from the IEEE Conference ' Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices ' We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770 ¿A/¿m at Ioff=100nA/¿m with VDD=1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded.
Cmos Integration Scheme
High Performance Cmos Devices
Cmos Integrated Circuits
Germanium Silicon Alloys
Compressive Stress Liner