Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack
By: Ernst, T.; Deleonibus, S.; Ghibaudo, G.; Faynot, O.; Rivallin, P.; Suhm, A.; Guillaumot, B.; Rivoire, M.; Hartmann, J.M.; Rabille, G.; Lafond, D.; Delaye, V.; Andrieu, F.; Borel, S.; Vizioz, C.; Toffoli, A.; De Crecy, F.; Barbe, J.C.; Maffini-Alvaro, V.; Ritzenthaler, R.; Bernard, E.; Isheden, C.; Dupre, C.;
2006 / IEEE / 1-4244-0438-X
This item was taken from the IEEE Conference ' Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack ' Three- and four-level matrices of 15×70 nm Si Nano-Beams have been integrated with a novel CMOS Gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5× higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated. (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (iii) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed.
Charge Carrier Processes
Transmission Line Matrix Methods
Gate All Around Process
Nanobeam Stacked Channels
3d Integration Process
Cmos Integrated Circuits