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An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks
By: Heh, D.; Lenahan, P.; Cochrane, C.; Choi, R.; Bersuker, G.; Young, C.; Jammy, R.; Neugroschel, A.; Lee, B.H.; Kang, C.Y.;
2006 / IEEE / 1-4244-0438-X
This item was taken from the IEEE Conference ' An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks ' Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (¿VTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.
Fast Transient Charging Contribution
Interface State Generation Process
High K Dielectric Materials
High-k Gate Dielectrics
Threshold Voltage Shift
High-k/sio2 Gate Stacks
Intrinsic Nbti Degradation Rate