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Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors

By: Lee, B.H.; Choi, R.; Nadkarni, S.; Young, C.D.; Park, C.S.; Sim, J.H.; Bersuker, G.;

2006 / IEEE / 0-7803-9498-4

Description

This item was taken from the IEEE Conference ' Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors ' Electron trapping in high-k gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the pre-existing defects (fast trapping) and temperature-activated migration of trapped electrons to unoccupied traps (slow trapping). The proposed model successfully describes low temperature threshold voltage instability in NMOS transistors with HfO2/TiN gate stacks.