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Detection of Electron Trap Generation due to Constant Voltage Stress on High-� Gate Stacks
By: Young, C.D.; Nadkarni, S.; Brown, G.A.; Zeitzoff, P.; Lee, B.H.; Vogel, E.; Barnett, J.; Bersuker, G.; Krishnan, S.A.; Sim, J.H.; Peterson, J.J.; Choi, R.; Harris, H.R.; Heh, D.;
2006 / IEEE / 0-7803-9498-4
This item was taken from the IEEE Conference ' Detection of Electron Trap Generation due to Constant Voltage Stress on High-� Gate Stacks ' Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO22/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-� gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown ""precursor"" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-¿ stacks.
High-k Gate Stacks Reliability
High K Dielectric Materials
High-k Gate Dielectrics
Threshold Voltage Instability
Charge Pumping Measurements
Positive Constant Voltage Stress
Electron Trap Generation
Semiconductor Device Reliability
Semiconductor Device Breakdown
High-k Dielectric Thin Films