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Detection of Trap Generation in High-� Gate Stacks due to Constant Voltage Stress

By: Choi, R.; Heh, D.; Young, C.D.; Bersuker, G.; Peterson, J.J.; Brown, G.A.; Zeitzoff, P.; Lee, B.H.; Barnett, J.;

2006 / IEEE / 1-4244-0181-4

Description

This item was taken from the IEEE Conference ' Detection of Trap Generation in High-� Gate Stacks due to Constant Voltage Stress ' Using a set of HfO2 gate stacks with different high-� and IL thicknesses, we have determined that the stress-generated electron traps are located primarily within the IL. This study indicates that the traps are generated on the ""precursor"" defect sites, presumably formed due to an interaction of the IL with the high-� film. Under the low voltage stress conditions of practical interest, these generated traps provide very limited contribution (compared to the pre-existing traps) to the threshold voltage instability.