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Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction

By: Jee, Y.J.; Hong, S.J.; Yon, G.H.; Park, T.; Buh, G.H.; Moon, J.T.; Kim, S.B.; Shin, Y.G.; Chung, U.-I.; Lee, J.W.; Yoo, J.R.; Ryoo, C.W.; Lee, J.S.;

2006 / IEEE / 1-4244-0047-3

Description

This item was taken from the IEEE Conference ' Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction ' Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced x-ray emission spectrometry (LEXES) and other conventional techniques such as Four Point Probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well.