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Interfacial layer dependence of HfSi/sub x/O/sub y/ gate stacks on V/sub T/ instability and charge trapping using ultra-short pulse I-V characterization [nMOS transistor experimentation]

By: Young, C.D.; Bersuker, G.; Brown, G.A.; Matthews, K.; Zhao, Y.; Zeitzoff, P.; Lee, B.H.; Sim, J.H.; Choi, R.;

2005 / IEEE / 0-7803-8803-8

Description

This item was taken from the IEEE Conference ' Interfacial layer dependence of HfSi/sub x/O/sub y/ gate stacks on V/sub T/ instability and charge trapping using ultra-short pulse I-V characterization [nMOS transistor experimentation] ' Fast transient charging was investigated using pulse I-V measurements with charging times ranging from 35 ns to 5 ms on HfSi/sub x/O/sub y/ gate stacks of varying interfacial layer thickness. It is shown that a nanosecond regime measurement capability is required to achieve trap-free pulse I-V characteristics. The ultra-short pulse I-V measurement technique and bias dependence was used to investigate fast transient charging. The fast electron trapping is found to be a source of degradation in the DC characteristics of the high-/spl kappa/ transistors, which strongly depends on the interfacial layer thickness.