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High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

By: Leobandung, E.; Nayakama, H.; Mocuta, D.; Miyamoto, K.; Angyal, M.; Meer, H.V.; McStay, K.; Ahsan, I.; Allen, S.; Azuma, A.; Belyansky, M.; Bentum, R.-V.; Cheng, J.; Chidambarrao, D.; Dirahoui, B.; Fukasawa, M.; Gerhardt, M.; Gribelyuk, M.; Halle, S.; Harifuchi, H.; Harmon, D.; Heaps-Nelson, J.; Hichri, H.; Ida, K.; Inohara, M.; Inouc, I.C.; Jenkins, K.; Kawamura, T.; Kim, B.; Ku, S.-K.; Kumar, M.; Lane, S.; Liebmann, L.; Logan, R.; Melville, I.; Miyashita, K.; Mocuta, A.; O'Neil, P.; Ng, M.-F.; Nogami, T.; Nomura, A.; Norris, C.; Nowak, E.; Ono, M.; Panda, S.; Penny, C.; Radens, C.; Ramachandran, R.; Ray, A.; Rhee, S.-H.; Ryan, D.; Shinohara, T.; Sudo, G.; Sugaya, F.; Strane, J.; Tan, Y.; Tsou, L.; Wang, L.; Wirbeleit, F.; Wu, S.; Yamashita, T.; Yan, H.; Ye, Q.; Yoneyama, D.; Zamdmer, D.; Zhong, H.; Zhu, H.; Zhu, W.; Agnello, P.; Bukofsky, S.; Bronner, G.; Crabbe, E.; Freeman, G.; Huang, S.-F.; Ivers, T.; Kuroda, H.; McHerron, D.; Pellerin, J.; Toyoshima, Y.; Subbanna, S.; Kepler, N.; Su, L.;

2005 / IEEE / 4-900784-00-1


This item was taken from the IEEE Conference ' High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell ' A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.