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Detection of trap generation in high-k gate stacks

By: Bersuker, G.; Young, C.D.; Zeitzoff, P.; Lee, B.H.; Vogel, E.; Barnett, J.; Brown, G.A.; Krishnan, S.A.; Sim, J.H.; Harris, H.R.; Peterson, J.J.; Choi, R.; Nadkarni, S.; Heh, D.;

2005 / IEEE / 0-7803-8992-1


This item was taken from the IEEE Conference ' Detection of trap generation in high-k gate stacks ' Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO/sub 2/ layer (IL) on the as-grown ""precursor"" defects most likely caused by the overlaying HfO/sub 2/ layer. These results point to the IL as a major focus for reliability improvement of high-k stacks.