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Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks
By: Harris, R.; Young, C.; Kirsch, P.D.; Choi, R.; Quevedo-Lopez, M.A.; Peterson, J.J.; Lee, J.C.; Krishnan, S.A.; Byoung Hun Lee; Hong-Jyh Li;
2005 / IEEE / 0-7803-8992-1
This item was taken from the IEEE Conference ' Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks ' Positive bias temperature instability (PBTI) is investigated in ultra-thin high-k films as a function of dielectric thickness on two different interfaces: SiO/sub 2/ and SiON. It is shown that charge trapping-induced threshold voltage (V/sub TH/) instability is exponentially dependent on dielectric thickness (or equivalent oxide thickness [EOT]) in the thickness range investigated. We propose that the significantly reduced charge trapping at thicknesses less than 2.0 nm is due to a change in the physical structure from suppressed crystallization at lesser thicknesses, resulting in reduced trap density. It is also observed that the SiON interface shows higher V/sub TH/ instability than the corresponding SiO/sub 2/ interface, while thickness dependence is the same for both.
Charge Trapping-induced Threshold Voltage Instability
Equivalent Oxide Thickness
High-k Gate Dielectrics
High K Dielectric Materials
Ultra-thin High-k Films
Positive Bias Temperature Instability
Charge Trapping Dependence
Atomic Layer Deposition
High-k Dielectric Thin Films
Ultra-thin Ald-hfsion/tin Gate Stacks