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Mobility enhancement of high-k gate stacks through reduced transient charging

By: Kirsch, P.D.; Sim, J.H.; Bersuker, G.; Ekerdt, J.G.; Wang, Q.; Majhi, P.; Moumen, N.; Lee, B.H.; Choi, R.; Young, C.D.; Quevedo-Lopez, M.; Li, H.J.; Peterson, J.; Krishnan, S.; Song, S.C.;

2005 / IEEE / 0-7803-9203-5

Description

This item was taken from the IEEE Conference ' Mobility enhancement of high-k gate stacks through reduced transient charging ' We report a high performance NFET with a HfO/sub 2//TiN gate stack showing high field (1 MV/cm) DC mobility of 194 cm/sup 2//V-s (80% univ. SiO/sub 2/) and peak DC mobility of 239 cm/sup 2//V-s at EOT=9.5/spl Aring/. These mobility results are among the best reported for HfO/sub 2/ with sub-10 /spl Aring/ EOT and represent a potential gate dielectric solution for 45 nm CMOS technologies. A 2/spl times/ mobility improvement was realized by thinning HfO/sub 2/ from T/sub phys/=4.0 nm to 2.0 nm. The mechanism for mobility improvement is shown to be reduced transient charge trapping. Issues associated with scaling HfO/sub 2/ including film continuity, density and growth incubation are studied with low energy ion scattering (LEIS), X-ray reflectivity (XRR) and Rutherford backscattering (RBS) and indicate atomic layer deposition (ALD) HfO/sub 2/ can scale below T/sub phys/= 2.0 nm. While the mobility advancement with 2.0 nm HfO/sub 2/ is important, an additional concurrent advancement is improved V/sub t/ stability. Constant voltage stress results show /spl Delta/V/sub t/ improves 2/spl times/ after 1000s stress at 1.8V as thickness is reduced in the range 2.0-4.0 nm.