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Effective minimization of charge trapping in high-k gate dielectrics with an ultra-short pulse technique
2004 / IEEE / 0-7803-8511-X
This item was taken from the IEEE Conference ' Effective minimization of charge trapping in high-k gate dielectrics with an ultra-short pulse technique ' An ultra-short pulse charge trapping characterization technique is introduced to study the charge-trapping effect in high-/spl kappa/ gate dielectrics. The system is capable of performing ""single pulse"" charge trapping measurement within several nanoseconds (ns) yielding near intrinsic characteristics of transistors with high-/spl kappa/ gate dielectrics with negligible charge trapping. It also characterizes transistors with high-/spl kappa/ gate dielectrics at close to operating frequency. The setup and capability of the system are described and its potential applications and benefits are discussed. We demonstrate using this technique where there appears to be no trapping with a pulse width less than 50ns and a significant increase in drive current is measured due to lack of charge trapping when comparing to DC I-V measurements for various high-/spl kappa/ gate stacks.
High-k Gate Dielectrics
Ultra-short Pulse Technique
Space Vector Pulse Width Modulation