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Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

By: Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; van Bentum, R.; Grasshoff, G.; Schwan, C.; Ehrichs, E.; Goad, S.; Buller, J.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.; Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, S.; Antreasyan, A.; Arnold, J.C.; Bandy, K.; Belyansky, M.; Bonnoit, A.; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, W.; Crowder, S.W.; Engel, B.; Harifuchi, H.; Huang, S.F.; Jagannathan, R.; Jamin, F.F.; Kohyama, Y.; Kuroda, H.; Lai, C.W.; Lee, H.K.; Lee, W.-H.; Lim, E.H.; Lai, W.; Mallikarjunan, A.; Matsumoto, K.; McKnight, A.; Nayak, J.; Ng, H.Y.; Panda, S.; Rengarajan, R.; Steigerwalt, M.; Subbanna, S.; Subramanian, K.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.; Toyoshima, Y.; Tran, P.; Wise, R.; Wong, R.; Yang, I.Y.; Wann, C.H.; Su, L.T.; Horstmann, M.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Salz, H.;

2004 / IEEE / 0-7803-8684-1

Description

This item was taken from the IEEE Conference ' Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing ' For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.