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High performance and low power transistors integrated in 65nm bulk CMOS technology

By: Luo, Z.; Steegen, A.; Wann, C.; Yang, I.; Sudijono, J.; Schiml, T.; Ku, J.; Rengarajan, R.; Weybright, M.; Zhu, H.; Lee, K.; Lin, Y.; Marokkey, S.; Zhang, B.; Kaltalioglu, E.; Kim, S.; Cowley, A.; Kim, K.; Chan, V.; Hook, T.; Vayshenker, A.; Coppock, C.; Vietzke, D.; Lian, J.; Eller, M.; Mann, R.; Baiocco, C.; Nguyen, P.; Kim, L.; Hoinkis, M.; Ku, V.; Klee, V.; Jamin, F.; Wrschka, P.; Shafer, P.; Lin, W.; Fang, S.; Ajmera, A.; Tan, W.; Park, D.; Mo, R.;

2004 / IEEE / 0-7803-8684-1

Description

This item was taken from the IEEE Conference ' High performance and low power transistors integrated in 65nm bulk CMOS technology ' This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node.