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Dual work function metal gate CMOS using CVD metal electrodes
By: Nakamura, K.; Li, Y.; McFeely, F.R.; Callegari, A.; Narayanan, V.; Shahidi, G.; Ieong, M.; Jammy, R.; Wann, C.; Ng, H.; Duch, F.; Sikorski, E.; Jamison, P.; Lacey, D.; Kawano, Y.; Wajda, C.; Gribelyuk, M.; Cabral, C., Jr.; Milkove, K.; Nguyen, P.; Ku, V.; Steegen, A.; Cartier, E.; Zafar, S.;
2004 / IEEE / 0-7803-8289-7
This item was taken from the IEEE Conference ' Dual work function metal gate CMOS using CVD metal electrodes ' Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO/sub 2/. T/sub inv/ as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole mobility has been obtained for aggressive stacks. It is further observed that electron mobility optimization is critically dependent on specific electrode and interface layer combinations along with post deposition processing even for nominally identical HfO/sub 2/ layers.
Research And Development
High-k Gate Dielectrics
High K Dielectric Materials
Electron Mobility Optimization
Cvd Metal Electrodes
Dual Work Function Metal Gate Cmos
Cmos Integrated Circuits