Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond
By: Shiga, K.; Yamada, T.; Ota, K.; Yamashita, T.; Ogura, M.; Kubota, M.; Kajiya, A.; Miyanaga, I.; Nakamura, M.; Hayashi, T.; Nakaoka, H.; Nakanishi, K.; Eriguchi, K.; Ohji, Y.; Inuishi, M.; Eimori, T.; Oda, H.; Umeda, H.;
2004 / IEEE / 0-7803-8289-7
This item was taken from the IEEE Conference ' Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond ' Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.
Low Standby Power
Low Operational Power
Gate-oxide Top Surface
65-nm Node Cmos
Integrated Circuit Reliability
Cmos Integrated Circuits