Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Integration issues of high-k gate stack: Process-induced charging

By: Barnett, J.; Gopalan, S.; Lee, B.H.; Moumen, N.; Chaudhary, N.; Gutt, J.; Bersuker, G.; Huff, H.R.; Murto, R.W.; Gardner, M.; Lysaght, P.; Sim, G.A.J.H.; Zeitzoff, P.M.; Li, H.-J.; Peterson, J.; Young, C.D.; Kim, Y.; Brown, G.;

2004 / IEEE / 0-7803-8315-X

Description

This item was taken from the IEEE Conference ' Integration issues of high-k gate stack: Process-induced charging ' Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.