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Interconnect modeling for copper/low-k technologies

By: Singh, A.; Bonifield, T.; Nagaraj, N.S.; Balsara, P.; Griesmer, R.;

2004 / IEEE / 0-7695-2072-3


This item was taken from the IEEE Conference ' Interconnect modeling for copper/low-k technologies ' Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. In this tutorial, four key aspects of copper/low-k interconnect process are discussed: Non-linear resistance, Selective Process Bias (SPB), dummy (fill) metal and process variations. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Techniques used in parasitic extraction to model the copper/low-k effects are discussed in detail. Techniques to measure resistance and capacitance in silicon and correlating them to parasitic extraction tools are presented to demonstrate systematic validation interconnect parasitics.