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Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer
By: Murto, R.W.; Larson, L.; Zeitzoff, P.; Bersuker, G.; Brown, G.A.; Gardner, M.; Agarwal, A.; Foran, B.; Barnett, J.; Matthews, K.; Young, C.D.; Lim, C.; Kim, Y.; Huff, H.R.; Kher, S.; Metzner, C.;
2003 / IEEE / 4-89114-033-X
This item was taken from the IEEE Conference ' Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer ' Conventional poly-Si gate MOS transistors with a high-k gate-dielectric were fabricated using a novel, ultra-thin Hf-oxide. Various integration effects on the high-k layer were studied such as Si-surface preparation, deposition conditions, and post-deposition anneals, demonstrating EOT of 1.6 to 1.2 nm and excellent gate leakage current. Promising transistor behaviors were obtained including electron mobility up to 90% of SiO/sub 2/ at both peak and high-field.
Equivalent Oxide Thickness
1.6 To 1.2 Nm
High-k Gate Dielectrics
High K Dielectric Materials
Gate Leakage Current
Ultrathin Hf-oxide Layer
Conventional Poly-si Gate Mos Transistors
Dielectric Thin Films
Semiconductor Device Measurement