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A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications

By: Zhang, K.; Thompson, S.; Bohr, M.; Zheng, B.; Ng, Y.; Ma, L.; Bhattacharya, U.;

2003 / IEEE / 4-89114-034-8

Description

This item was taken from the IEEE Conference ' A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications ' A 50 Mb SRAM chip is designed and fabricated on an industry leading 90 nm CMOS technology that features a 1 /spl mu/m/sup 2/ SRAM cell and 50 nm gate length transistors with strained silicon. The SRAM chip is formed with 100/spl times/512 Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.