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Backend process optimization for 90 nm high-density ASIC chips

By: Zarkesh-Ha, P.; Lynch, W.; Loh, W.; Cheng, C.-C.; Lakshminarayanan, S.; Wright, P.;

2003 / IEEE / 0-7803-7797-4

Description

This item was taken from the IEEE Conference ' Backend process optimization for 90 nm high-density ASIC chips ' Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 /spl mu/m for the higher levels of metal.