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A systematic approach to interconnect modeling and process monitoring

By: Kulkarni, M.; Nagaraj, N.S.; Zabierek, C.; Hossain, I.; Usha Narasimha; Bonifield, T.;

2003 / IEEE / 0-7803-7797-4

Description

This item was taken from the IEEE Conference ' A systematic approach to interconnect modeling and process monitoring ' This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.